Forum Discussion
amildm
Contributor
ContributorCyclone 10 PLLs -> downscale clocks -> how much possible?
Hi All,
I'm working with Cyclone 10 GX, which has a reference clock of 100MHz .
What lowest frequency could I reach with PLLs using this clock as a reference clock?
I've tried to play ...
- Hello,
minimal output frequency is definer bei VCO frequency range and output divider factor. It's about 0.6 MHz. Lower frequencies can be achieved with frequency divider in core logic.
NazrulNaim_Intel
Regular Contributor
Regular ContributorHi,
Thank you for reaching out. Allow me some time to look into your issue. I shall come back to you with findings.
Thank you for your patience.
Best Regards,
Nazrul Naim
