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amildm's avatar
amildm
Icon for Contributor rankContributor
3 years ago
Solved

Cyclone 10 PLLs -> downscale clocks -> how much possible?

Hi All, I'm working with Cyclone 10 GX, which has a reference clock of 100MHz . What lowest frequency could I reach with PLLs using this clock as a reference clock? I've tried to play ...
  • FvM's avatar
    FvM
    3 years ago
    Hello,
    minimal output frequency is definer bei VCO frequency range and output divider factor. It's about 0.6 MHz. Lower frequencies can be achieved with frequency divider in core logic.
NazrulNaim_Intel's avatar
NazrulNaim_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


As per the answer provided by user named 'FvM'. The answer can be accepted. Lower frequencies can be achieved with frequency divider in core logic.


Regards,

Nazrul Naim