Critical warning about asynchronous clock domains from same PLL

Hey there,

I have an FPGA design where a part is running at 150MHz and one part is running with 75MHz (both sourced from the same PLL). So, IMHO the clocks should be synchronous.

Of course I need to bring data from one clock domain to another clock domain and I am using a 2FF synchronizer. I already did this also in other designs (eg. MAX10) and AFAIR it worked flawlessly.

Now I have a Cyclone IV-FPGA and during synthesis I get a critical warning D101: Data bits are not synchronized when transferred between asynchronous clock domains...

My SDC-file has the following entries:

set_time_format -unit ns -decimal_places 3
create_clock -name {clk_ext} -period 50.000 -waveform { 0.000 25.000 } 
derive_pll_clocks
derive_clock_uncertainty 

I think everything should work, but it isn't :-/

Has anybody an idea what is going wrong here?

Thank you!

Regards

Mathias