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Honored Contributor
Honored ContributorCritical warning about asynchronous clock domains from same PLL
Hey there, I have an FPGA design where a part is running at 150MHz and one part is running with 75MHz (both sourced from the same PLL). So, IMHO the clocks should be synchronous. Of course...
Altera_ForumHonored Contributor
Honored ContributorIt is clear that tool regarded clk[0] @150Mhz & clk[1] @75MHz as asynchronous for some reason. It could be they are not in phase or pll mode may be dictating that...
So regard it as asynchronous and then you have to cross domains based on double synchronisers. But you did say you done that, or have you done that properly as the reported paths deny it.
