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Altera_Forum
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8 years ago

Critical warning about asynchronous clock domains from same PLL

Hey there, I have an FPGA design where a part is running at 150MHz and one part is running with 75MHz (both sourced from the same PLL). So, IMHO the clocks should be synchronous. Of course...
Altera_Forum's avatar
Altera_Forum
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8 years ago

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It is strange that the tool reports unrelated clocks. Any reason why duty cycle is 50/1 on each clock??

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I don't know, I think this happens due to the write_sdc -expand command. My original SDC-file does not contain these lines (see my first post).

But looking in the documentation of SDC Commands (https://www.altera.com/en_us/pdfs/literature/manual/mnl_sdctmq.pdf) at page 2-8: duty_cycle is given in percent, so I think this value corresponds to 50% duty cycle. I think this is OK. Looking in the compilation report states also that the duty cycle is 50.00 for each PLL generated clock. IMHO this is not a problem.