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Altera_Forum's avatar
Altera_Forum
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8 years ago

Critical warning about asynchronous clock domains from same PLL

Hey there, I have an FPGA design where a part is running at 150MHz and one part is running with 75MHz (both sourced from the same PLL). So, IMHO the clocks should be synchronous. Of course...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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I don't know where the *pll1* is coming from, but in the compilation report under Flow Summary Quartus states that 1/4 (25%) of the PLLs are used. I also don't have any command about unrelated clocks in the sdc. You can also have a look at my other post where I did a write_sdc -expand (Result: https://pastebin.com/dhefpn2e)

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It is strange that the tool reports unrelated clocks. Any reason why duty cycle is 50/1 on each clock??