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Altera_Forum's avatar
Altera_Forum
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8 years ago

Critical warning about asynchronous clock domains from same PLL

Hey there, I have an FPGA design where a part is running at 150MHz and one part is running with 75MHz (both sourced from the same PLL). So, IMHO the clocks should be synchronous. Of course...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

As far as I see I do not have any strange settings in the PLL. I will ignore this warnings and I will see, if my design fails sometime.

Thank you for your ideas and hints :)