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Altera_Forum
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18 years ago

critical path:70% IC delay + 30% CELL delay

I hope my system can run at 100MHz.

After full compilation, the timing report show me that fmax<80MHz.

And I found that the critical path contain 70% IC delay + 30% CELL delay,pls see below: 


Info: Slack time is -11.725 ns for clock "clk" between source register "FreqMeasure_NiosII:inst|jtag_debug_module_pipeline_bridge:the_jtag_debug_module_pipeline_bridge|jtag_debug_module_pipeline_bridge_downstream_adapter:the_jtag_debug_module_pipeline_bridge_downstream_adapter|m1_address" and destination register "FreqMeasure_NiosII:inst|freqmeasure_avaloninterface_inst:the_freqmeasure_avaloninterface_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|avs_freqmeasure_slave_readdata"
	Info: Fmax is 54.37 MHz (period= 18.391 ns)
	Info: + Largest register to register requirement is 6.347 ns
		Info: + Setup relationship between source and destination is 6.666 ns
			Info: + Latch edge is 6.666 ns
				Info: Clock period of Destination clock "clk" is 6.666 ns with  offset of 0.000 ns and duty cycle of 50
				Info: Multicycle Setup factor for Destination register is 1
			Info: - Launch edge is 0.000 ns
				Info: Clock period of Source clock "clk" is 6.666 ns with  offset of 0.000 ns and duty cycle of 50
				Info: Multicycle Setup factor for Source register is 1
		Info: + Largest clock skew is -0.055 ns
			Info: + Shortest clock path from clock "clk" to destination register is 3.256 ns
				Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_T2; Fanout = 2; CLK Node = 'clk'
				Info: 2: + IC(0.135 ns) + CELL(0.000 ns) = 1.235 ns; Loc. = CLKCTRL_G3; Fanout = 23640; COMB Node = 'clk~clkctrl'
				Info: 3: + IC(1.355 ns) + CELL(0.666 ns) = 3.256 ns; Loc. = LCFF_X54_Y13_N23; Fanout = 1; REG Node = 'FreqMeasure_NiosII:inst|freqmeasure_avaloninterface_inst:the_freqmeasure_avaloninterface_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|avs_freqmeasure_slave_readdata'
				Info: Total cell delay = 1.766 ns ( 54.24 % )
				Info: Total interconnect delay = 1.490 ns ( 45.76 % )
			Info: - Longest clock path from clock "clk" to source register is 3.311 ns
				Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_T2; Fanout = 2; CLK Node = 'clk'
				Info: 2: + IC(0.135 ns) + CELL(0.000 ns) = 1.235 ns; Loc. = CLKCTRL_G3; Fanout = 23640; COMB Node = 'clk~clkctrl'
				Info: 3: + IC(1.410 ns) + CELL(0.666 ns) = 3.311 ns; Loc. = LCFF_X52_Y32_N9; Fanout = 1431; REG Node = 'FreqMeasure_NiosII:inst|jtag_debug_module_pipeline_bridge:the_jtag_debug_module_pipeline_bridge|jtag_debug_module_pipeline_bridge_downstream_adapter:the_jtag_debug_module_pipeline_bridge_downstream_adapter|m1_address'
				Info: Total cell delay = 1.766 ns ( 53.34 % )
				Info: Total interconnect delay = 1.545 ns ( 46.66 % )
		Info: - Micro clock to output delay of source is 0.304 ns
		Info: - Micro setup delay of destination is -0.040 ns
	Info: - Longest register to register delay is 18.072 ns
		Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X52_Y32_N9; Fanout = 1431; REG Node = 'FreqMeasure_NiosII:inst|jtag_debug_module_pipeline_bridge:the_jtag_debug_module_pipeline_bridge|jtag_debug_module_pipeline_bridge_downstream_adapter:the_jtag_debug_module_pipeline_bridge_downstream_adapter|m1_address'
		Info: 2: + IC(3.079 ns) + CELL(0.589 ns) = 3.668 ns; Loc. = LCCOMB_X63_Y45_N2; Fanout = 1; COMB Node = 'FreqMeasure_NiosII:inst|freqmeasure_avaloninterface_inst:the_freqmeasure_avaloninterface_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|Mux45~2194'
		Info: 3: + IC(3.565 ns) + CELL(0.206 ns) = 7.439 ns; Loc. = LCCOMB_X21_Y42_N0; Fanout = 1; COMB Node = 'FreqMeasure_NiosII:inst|freqmeasure_avaloninterface_inst:the_freqmeasure_avaloninterface_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|Mux45~2195'
		Info: 4: + IC(0.360 ns) + CELL(0.206 ns) = 8.005 ns; Loc. = LCCOMB_X21_Y42_N14; Fanout = 1; COMB Node = 'FreqMeasure_NiosII:inst|freqmeasure_avaloninterface_inst:the_freqmeasure_avaloninterface_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|Mux45~2196'
		Info: 5: + IC(0.364 ns) + CELL(0.366 ns) = 8.735 ns; Loc. = LCCOMB_X21_Y42_N26; Fanout = 1; COMB Node = 'FreqMeasure_NiosII:inst|freqmeasure_avaloninterface_inst:the_freqmeasure_avaloninterface_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|Mux45~2199'
		Info: 6: + IC(1.872 ns) + CELL(0.370 ns) = 10.977 ns; Loc. = LCCOMB_X15_Y46_N8; Fanout = 1; COMB Node = 'FreqMeasure_NiosII:inst|freqmeasure_avaloninterface_inst:the_freqmeasure_avaloninterface_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|Mux45~2200'
		Info: 7: + IC(0.377 ns) + CELL(0.370 ns) = 11.724 ns; Loc. = LCCOMB_X15_Y46_N18; Fanout = 1; COMB Node = 'FreqMeasure_NiosII:inst|freqmeasure_avaloninterface_inst:the_freqmeasure_avaloninterface_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|Mux45~2211'
		Info: 8: + IC(3.381 ns) + CELL(0.370 ns) = 15.475 ns; Loc. = LCCOMB_X33_Y19_N16; Fanout = 1; COMB Node = 'FreqMeasure_NiosII:inst|freqmeasure_avaloninterface_inst:the_freqmeasure_avaloninterface_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|Mux45~2339'
		Info: 9: + IC(2.283 ns) + CELL(0.206 ns) = 17.964 ns; Loc. = LCCOMB_X54_Y13_N22; Fanout = 1; COMB Node = 'FreqMeasure_NiosII:inst|freqmeasure_avaloninterface_inst:the_freqmeasure_avaloninterface_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|avs_freqmeasure_slave_readdata~10805'
		Info: 10: + IC(0.000 ns) + CELL(0.108 ns) = 18.072 ns; Loc. = LCFF_X54_Y13_N23; Fanout = 1; REG Node = 'FreqMeasure_NiosII:inst|freqmeasure_avaloninterface_inst:the_freqmeasure_avaloninterface_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|avs_freqmeasure_slave_readdata'
		Info: Total cell delay = 2.791 ns ( 15.44 % )
		Info: Total interconnect delay = 15.281 ns ( 84.56 % )

pls note:

Info: Total cell delay = 2.791 ns ( 15.44 % )

Info: Total interconnect delay = 15.281 ns ( 84.56 % )

anybody guide me how to improve it?

Thanks in advance!

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Try the fmax recommendations at "Tools --> Advisors --> Timing Optimization Advisor".

    The Stage 3 recommendations include a couple of suggestions for manually controlling the placement. Before doing that, remove any user location assignment or LogicLock regions that you already have to see whether they are hurting performance.

    If the failing path is in a huge segment of the Avalon bus, it might be that some of the paths have to be stretched out as far as in the example you posted.

    I see jtag_debug_module_pipeline_bridge in your path. If you put in a pipeline bridge yourself, you might not have done it in the best way. I recently saw something saying to review all the documentation, probably in the Quartus handbook, on the Avalon bridges to be sure they are implemented correctly to help performance.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi David,

    maybe I'm wrong, but according to your timing report you have used 150 MHz (6.66666ns)

    as clock constraint. Overconstraining a design leads often to worse timing results. If you would like to achieve only 100MHz , try to use 100MHz as clock setting.

    Kind regards

    Gerd
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Thanks for both of you...

    Yes, it's overconstraining. But it isn't the root reason led to the result.

    I have found the reason, it's hard to decribe, but I will try:

    My IP has 360 channel of sub-module, they are the same module which has two 32-bit registers. After compilation, custom IP allocate over 80% of FPGA resource which mean that custom IP's registers distribute all over the FPGA.

    NiosII CPU need read value of register's of selected channel indexed by address bus. So there exist because address register and slavedata register. As above described, slavedata registers distribute all over the FPGA, so the critical path showed above is reasonable and can't be eliminated.

    I think What I should do is the following two steps:

    1. In SOPC Builder component editor, configurate suitable setup time and wait time for my custom IP

    2. In QuartusII, set multicycle constraint for the path from address register to slavedata register

    Am I right?

    m1_address[10]" and destination register "FreqMeasure_NiosII:inst|freqmeasure_avaloninterface_inst:the_freqmeasure_avaloninterface_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|avs_freqmeasure_slave_readdata[18]
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Thanks for both of you...

    Yes, it's overconstraining. But it isn't the root reason led to the result.

    I have found the reason, it's hard to decribe, but I will try:

    My IP has 360 channel of sub-module, they are the same module which has two 32-bit registers. After compilation, custom IP allocate over 80% of FPGA resource which mean that custom IP's registers distribute all over the FPGA.

    NiosII CPU need read back value of register's from selected channel indexed by address bus. The value of register's from selected channel is read back throught slavedata register; So there exist paths between address registers and slavedata registers. As above described, slavedata registers distribute all over the FPGA, so the critical path showed above is reasonable and can't be eliminated.

    I think What I should do is the following two steps:

    1. In SOPC Builder component editor, configurate suitable setup time and wait time for my custom IP

    2. In QuartusII, set multicycle constraint for the path from address register to slavedata register

    Am I right?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hi David,

    if you can spend more time for reading the data a multicycle constraint should be ok.

    Kind regards

    Gerd
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Could you guide me where can I find the related information?

    Is it in any handbook of Altera?
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi David,

    you can use the build-in Help of Quartus II. If you need more information you should download the QuartusII Handbook from the Altera Web-site.

    Kind regards

    Gerd
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    --- Quote Start ---

    I have found the reason, it's hard to decribe, but I will try:

    My IP has 360 channel of sub-module, they are the same module which has two 32-bit registers. After compilation, custom IP allocate over 80% of FPGA resource which mean that custom IP's registers distribute all over the FPGA.

    NiosII CPU need read back value of register's from selected channel indexed by address bus. The value of register's from selected channel is read back throught slavedata register; So there exist paths between address registers and slavedata registers. As above described, slavedata registers distribute all over the FPGA, so the critical path showed above is reasonable and can't be eliminated.

    I think What I should do is the following two steps:

    1. In SOPC Builder component editor, configurate suitable setup time and wait time for my custom IP

    2. In QuartusII, set multicycle constraint for the path from address register to slavedata register

    --- Quote End ---

    My Question is how to set the setup time/wait time/pipelined transfer read latency for my custom IP in component editor basing on the set_multicycle_path command.

    I have done the following setting in timequest: 

    set_multicycle_path -setup -end -from   *|freqmeasure_wholesystem:*|s_SelectCounter }]  -to   }] 3
set_multicycle_path -hold -end -from   *|freqmeasure_wholesystem:*|s_SelectCounter }]  -to   }] 1

    NOTE: 

    
s_SelectCounter <= avs_freqmeasure_slave_address(0)
s_SelectChannel <= avs_freqmeasure_slave_address(avs_freqmeasure_slave_address'high downto 1)

    basing on the parameters above, I set:

    setup time = 1;we need one clock to push address to s_SelectCounter & s_SelectChannel

    wait time = 1;euqal to multicycle_hold_value

    pipelined transfer read latency = 1;equal to multicycle_period_value-multicycle_hold_value-1

    Above is basing on my own thought, waiting & welcome any correction.