critical path:70% IC delay + 30% CELL delay

Thanks for both of you...

Yes, it's overconstraining. But it isn't the root reason led to the result.

I have found the reason, it's hard to decribe, but I will try:

My IP has 360 channel of sub-module, they are the same module which has two 32-bit registers. After compilation, custom IP allocate over 80% of FPGA resource which mean that custom IP's registers distribute all over the FPGA.

NiosII CPU need read back value of register's from selected channel indexed by address bus. The value of register's from selected channel is read back throught slavedata register; So there exist paths between address registers and slavedata registers. As above described, slavedata registers distribute all over the FPGA, so the critical path showed above is reasonable and can't be eliminated.

I think What I should do is the following two steps:

1. In SOPC Builder component editor, configurate suitable setup time and wait time for my custom IP

2. In QuartusII, set multicycle constraint for the path from address register to slavedata register

Am I right?