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Altera_Forum
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18 years ago

critical path:70% IC delay + 30% CELL delay

I hope my system can run at 100MHz. After full compilation, the timing report show me that fmax<80MHz. And I found that the critical path contain 70% IC delay + 30% CELL delay,pls see below: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi David,

maybe I'm wrong, but according to your timing report you have used 150 MHz (6.66666ns)

as clock constraint. Overconstraining a design leads often to worse timing results. If you would like to achieve only 100MHz , try to use 100MHz as clock setting.

Kind regards

Gerd