critical path:70% IC delay + 30% CELL delay

Try the fmax recommendations at "Tools --> Advisors --> Timing Optimization Advisor".

The Stage 3 recommendations include a couple of suggestions for manually controlling the placement. Before doing that, remove any user location assignment or LogicLock regions that you already have to see whether they are hurting performance.

If the failing path is in a huge segment of the Avalon bus, it might be that some of the paths have to be stretched out as far as in the example you posted.

I see jtag_debug_module_pipeline_bridge in your path. If you put in a pipeline bridge yourself, you might not have done it in the best way. I recently saw something saying to review all the documentation, probably in the Quartus handbook, on the Avalon bridges to be sure they are implemented correctly to help performance.