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I have found the reason, it's hard to decribe, but I will try:
My IP has 360 channel of sub-module, they are the same module which has two 32-bit registers. After compilation, custom IP allocate over 80% of FPGA resource which mean that custom IP's registers distribute all over the FPGA.
NiosII CPU need read back value of register's from selected channel indexed by address bus. The value of register's from selected channel is read back throught slavedata register; So there exist paths between address registers and slavedata registers. As above described, slavedata registers distribute all over the FPGA, so the critical path showed above is reasonable and can't be eliminated.
I think What I should do is the following two steps:
1. In SOPC Builder component editor, configurate suitable setup time and wait time for my custom IP
2. In QuartusII, set multicycle constraint for the path from address register to slavedata register
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My Question is how to set the setup time/wait time/pipelined transfer read latency for my custom IP in component editor basing on the set_multicycle_path command.
I have done the following setting in timequest:
set_multicycle_path -setup -end -from *|freqmeasure_wholesystem:*|s_SelectCounter }] -to }] 3
set_multicycle_path -hold -end -from *|freqmeasure_wholesystem:*|s_SelectCounter }] -to }] 1
NOTE:
s_SelectCounter <= avs_freqmeasure_slave_address(0)
s_SelectChannel <= avs_freqmeasure_slave_address(avs_freqmeasure_slave_address'high downto 1)
basing on the parameters above, I set:
setup time = 1;we need one clock to push address to s_SelectCounter & s_SelectChannel
wait time = 1;euqal to multicycle_hold_value
pipelined transfer read latency = 1;equal to multicycle_period_value-multicycle_hold_value-1
Above is basing on my own thought, waiting & welcome any correction.
Honored Contributor
