Altera_ForumHonored Contributor18 years agocritical path:70% IC delay + 30% CELL delay I hope my system can run at 100MHz. After full compilation, the timing report show me that fmax<80MHz. And I found that the critical path contain 70% IC delay + 30% CELL delay,pls see below: ...Show More
Recent DiscussionsQuartus Lite 23.1 MAX 10 EncryptionHow to fix Error(23782): Failed to find an expected reportSolvedMailbox Client IP - SEND_CERTIFICATE command through FPGA fabricQuartus Prime license rehosted, unable to runFailed to run ip-setup-simulation: