Creating an Avalon Master - Please Help

Hi notme:

It depends on what you are doing.

First You'll want to read the Avalon bus specification:

www.altera.com/literature/manual/mnl_avalon_spec.pd

And define your master device in verilog/vhdl.

If you are just hooking this up to the NIOS CPU, the CPU has a master port already, so you don't have to create your own, but if you are hooking it up to some other CPU and/or dedicated logic, the master connectivity is defined by the spec. However there are several valid master types, so you'll should read though it and understand what you need.

Once you have the the Master component defined, you go into SOPC builder, and define the component. This basically tells SOPC builder what signals are Avalon/clock/reset/etc, and what signals are exports that go to the top of the SOPC system. Once this is done, you can add the component to your SOPC system.

Now with SOPC builder, you have connectivity between various master and slave devices that you can click on. Once completed, you generate the modules, and it produces a SOPC level that you can import into your top module and finish any non-sopc connectivity.

(IE it generates all the arbiters/muxes/domain crossing logic necessary depending on the complexity of the system)

Pete

Once you mast

Thanks for Post. I am still a bit confused. I have an external micro that I want to connect to the SDR Dram controller in SOPC. For this I need an Avalon master. I have made a few attempts at this but am not sure about a few things....

1. How do I know which Avalon signals the DRAM IP requires. I have looked at the docs and they dont say???

2. Do I then define the external micros address,data and control lines in my component as "export" signals in SOPC?

3. Is there a recommended method of connecting my address,data and control lines to the Avalon address,data and control lines?

Hi notme:

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1. How do I know which Avalon signals the DRAM IP requires. I have looked at the docs and they dont say???

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You can bet the DRAM IP Is a slave with byteenables. However there are various types of slaves, Most likely it will have a data valid as well. However, the exact inter-connectivity will be handled by SOPCbuilder. You just need to make sure your Master supports byteenables if you need to do transactions less than a full word. If you only due word sized transactions, you may due bursting, but care should be done to insure you align your allowed burst size and address alignment, so that the you don't have unintended line-wraps.

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2. Do I then define the external micros address,data and control lines in my component as "export" signals in SOPC?

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Yes.

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3. Is there a recommended method of connecting my address,data and control lines to the Avalon address,data and control lines?

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Not really, It's usually a depends on the uP. Like with TI, you have an EMIF bus, so the timing/strobe is slightly different, a bit of logic to interface the too, but it isn't too significant. Once you have the "Bridge" from your CPU to Avalon interface, you can then click on any avalon slave device to the bus and SOPC builder handles all the interconnect.

Thanks -

I have tried that but SOPC gives warning like.... m0 Must have address signal. Which address signal is it talking about? The signals going to the Avalon slave dram controller or the signal going to my external cpu?

Perhaps you could clarify the signals.. My external address bus is in the Name column, what should be in the Interface column? There is a drop down with many options, should this be the export_0 option?

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Thanks -

I have tried that but SOPC gives warning like.... m0 Must have address signal. Which address signal is it talking about? The signals going to the Avalon slave dram controller or the signal going to my external cpu?

Perhaps you could clarify the signals.. My external address bus is in the Name column, what should be in the Interface column? There is a drop down with many options, should this be the export_0 option?

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In you Bridge interface between your CPU and Avalon bus, you should have as a minimum the following Avalon master should have a minimum of : clk waitrequest Address, ReadData, Writedata, read and write signals. These should be defined under the Avalon Master type.

The CPU interface signasl, which depending on the CPU type may include Address, Data, read and Write signals as well, will all be defined as export signals.

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Oops.. back sooner than expected. Where can I find info regarding the signal timing between the Avalon master and external cpu's? I have looked at the Avalon specs but the timing all seems to be between master and slave devices and not between master and external devices

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You cannot directly connect an external device with the Avalon Master. You need to create a Tri-state bridge before you can connect the device to the bus.

As for the signals, the signals that you need are: clk, bidirectional data, address, chipselect, write, read and byteenable. Further the addressing can be Register Slave Addressing (if it is a simple storage or data-logging memory) or Memory Slave Addressing (if it is sth like a cpu memory). Specify appropriate Read Wait, Write Wait:and Hold and Setup cycles. And you are done!

For Connecting your external micro with SDRAM controller core, u need to define the Avalon tristate master port with the signals from micro and connect this to the tristate slave port of avalon tristate bridge using sopc builder. The master port of the avalon tristate bridge should be connected to the avalon slave port of the SDRAM controller. So you will be having three components in your sopc builder

1) uc Wrapper with Avalon tristate Master port

2) Avalon tristate master bridge and [Avalon tristate bridge will have Avalon tristate master and Avalon MM master]

3) SDRAM controller core with Avalon MM Slave port

You need to allocate the address space for SDRAM while parametrizing the SDRAM controller.