Honored Contributor
Honored ContributorHi notme:
It depends on what you are doing. First You'll want to read the Avalon bus specification: www.altera.com/literature/manual/mnl_avalon_spec.pd And define your master device in verilog/vhdl. If you are just hooking this up to the NIOS CPU, the CPU has a master port already, so you don't have to create your own, but if you are hooking it up to some other CPU and/or dedicated logic, the master connectivity is defined by the spec. However there are several valid master types, so you'll should read though it and understand what you need. Once you have the the Master component defined, you go into SOPC builder, and define the component. This basically tells SOPC builder what signals are Avalon/clock/reset/etc, and what signals are exports that go to the top of the SOPC system. Once this is done, you can add the component to your SOPC system. Now with SOPC builder, you have connectivity between various master and slave devices that you can click on. Once completed, you generate the modules, and it produces a SOPC level that you can import into your top module and finish any non-sopc connectivity. (IE it generates all the arbiters/muxes/domain crossing logic necessary depending on the complexity of the system) Pete Once you mast
