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Thanks -
I have tried that but SOPC gives warning like.... m0 Must have address signal. Which address signal is it talking about? The signals going to the Avalon slave dram controller or the signal going to my external cpu?
Perhaps you could clarify the signals.. My external address bus is in the Name column, what should be in the Interface column? There is a drop down with many options, should this be the export_0 option?
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In you Bridge interface between your CPU and Avalon bus, you should have as a minimum the following Avalon master should have a minimum of : clk waitrequest Address, ReadData, Writedata, read and write signals. These should be defined under the Avalon Master type.
The CPU interface signasl, which depending on the CPU type may include Address, Data, read and Write signals as well, will all be defined as export signals.
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