Honored Contributor
Honored ContributorHi notme:
--- Quote Start --- 1. How do I know which Avalon signals the DRAM IP requires. I have looked at the docs and they dont say??? --- Quote End --- You can bet the DRAM IP Is a slave with byteenables. However there are various types of slaves, Most likely it will have a data valid as well. However, the exact inter-connectivity will be handled by SOPCbuilder. You just need to make sure your Master supports byteenables if you need to do transactions less than a full word. If you only due word sized transactions, you may due bursting, but care should be done to insure you align your allowed burst size and address alignment, so that the you don't have unintended line-wraps. --- Quote Start --- 2. Do I then define the external micros address,data and control lines in my component as "export" signals in SOPC? --- Quote End --- Yes. --- Quote Start --- 3. Is there a recommended method of connecting my address,data and control lines to the Avalon address,data and control lines? --- Quote End --- Not really, It's usually a depends on the uP. Like with TI, you have an EMIF bus, so the timing/strobe is slightly different, a bit of logic to interface the too, but it isn't too significant. Once you have the "Bridge" from your CPU to Avalon interface, you can then click on any avalon slave device to the bus and SOPC builder handles all the interconnect.
