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Oops.. back sooner than expected. Where can I find info regarding the signal timing between the Avalon master and external cpu's? I have looked at the Avalon specs but the timing all seems to be between master and slave devices and not between master and external devices
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You cannot directly connect an external device with the Avalon Master. You need to create a Tri-state bridge before you can connect the device to the bus.
As for the signals, the signals that you need are: clk, bidirectional data, address, chipselect, write, read and byteenable. Further the addressing can be Register Slave Addressing (if it is a simple storage or data-logging memory) or Memory Slave Addressing (if it is sth like a cpu memory). Specify appropriate Read Wait, Write Wait:and Hold and Setup cycles. And you are done!
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