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Honored Contributor
Honored ContributorConversion error (integer to std_logic_vector) "Undefined symbol 'to_signed'"
Hello everyone!
I'm just starting into VHDL programming and I've been asked to make a 0 to 999 counter (as BCD incrementor Suggested Experiment 3.9.3 in FPGA Prototyping by VHDL Examples by Pong P.Chu ), since I'm not such a good programmer I decided to do it first from 0 to 9, so I wanted to try it with this code here:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity BCD_Increm is
Port ( i : in STD_LOGIC; -- using it as a pushbutton to increment the counting
unit : out STD_LOGIC_VECTOR(3 DOWNTO 0));
end BCD_Increm;
architecture BCD_arch of BCD_Incr is
signal un : integer;
signal u : std_logic_vector(3 downto 0);
signal usi : signed (3 downto 0);
begin
un<='0'; -- starts with 'units' in 0's
unit <= u;
process(i,un)
begin
if (i=1) then -- check if pushbutton is 'on'
if (un <= 9) then -- check if units is less than or equal to 9
un <= un + 1; -- if so, then add 1 to units
usi <= to_signed(un,4); -- convert to signed
u <= std_logic_vector(usi(3 downto 0)); --convert to std_logic_vector
else
un <= 0; -- if units is greater than 9 then units are 0
usi <= to_signed(un,4); -- convert to signed
u <= std_logic_vector(usi(3 downto 0)); -- convert to std_logic_vector
end if;
else
un <= un; --if pushbutton is not 'on' then keep the same value for units
usi <= to_signed(un,4); -- convert to signed
u <= std_logic_vector(usi(3 downto 0)); --convert to std_logic_vector
end if;
end process;
end BCD_arch;
Line 47. Undefined symbol 'to_signed'.
Line 47. to_signed: Undefined symbol (last report in this block)
Line 48. usi: Undefined symbol (last report in this block)
