Conversion error (integer to std_logic_vector) "Undefined symbol 'to_signed'"

Can't see anything wrong with that code. Is it a particularly old version of ise? Btw, this is an altera forum, ise is a xilinx product (altera competitor).

Elsewhere there are issues. You're missing using from the sensitive list. And your code creates a latch because your asynchronous circuit stores a value when I isn't 1. These are undesirable in FPGAs.

Finally, you have an adder on un. This will not work as it will try and increment in 0 time infinitely. You need a clock to run a counter.