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Altera_Forum
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9 years ago

Conversion error (integer to std_logic_vector) "Undefined symbol 'to_signed'"

Hello everyone! I'm just starting into VHDL programming and I've been asked to make a 0 to 999 counter (as BCD incrementor Suggested Experiment 3.9.3 in FPGA Prototyping by VHDL Examples by Po...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Add use ieee.std_logic_signed.all; along with what you have and recompile and let's get the feedback.

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Dont do this - because std_logic_signed is not a standard VHDL library.

You should use numeric_std for arithmatic (as the OP has done).