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Honored Contributor
Honored ContributorConversion error (integer to std_logic_vector) "Undefined symbol 'to_signed'"
Hello everyone! I'm just starting into VHDL programming and I've been asked to make a 0 to 999 counter (as BCD incrementor Suggested Experiment 3.9.3 in FPGA Prototyping by VHDL Examples by Po...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Add use ieee.std_logic_signed.all; along with what you have and recompile and let's get the feedback. --- Quote End --- Dont do this - because std_logic_signed is not a standard VHDL library. You should use numeric_std for arithmatic (as the OP has done).
