--- Quote Start ---
Can't see anything wrong with that code. Is it a particularly old version of ise? Btw, this is an altera forum, ise is a xilinx product (altera competitor).
Elsewhere there are issues. You're missing using from the sensitive list. And your code creates a latch because your asynchronous circuit stores a value when I isn't 1. These are undesirable in FPGAs.
Finally, you have an adder on un. This will not work as it will try and increment in 0 time infinitely. You need a clock to run a counter.
--- Quote End ---
Thanks for your answer, and I'm terribly sorry for my mistake, I just googled forums about VHDL programing and since I remembered professor said something about Altera so I signed in here, but it won't happen again :oops:.
About the code, the version I'm working with is the new one, so as I understood, I must write 'usi' in the sensitive list, too, right? I'm still a little confuse about the adder situation here, and since we are not allow to use something we haven't seen in the chapter that's why I didn't make it with a clock, but I'll try it anyway, thanks
Honored Contributor
