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Altera_Forum
Honored Contributor
10 years agoConversion error (integer to std_logic_vector) "Undefined symbol 'to_signed'"
Hello everyone! I'm just starting into VHDL programming and I've been asked to make a 0 to 999 counter (as BCD incrementor Suggested Experiment 3.9.3 in FPGA Prototyping by VHDL Examples by Po...
Altera_Forum
Honored Contributor
10 years agoHi x_ao28,
I have noticed these with your code: --- Quote Start --- signal un : integer; . . . un<='0'; -- starts with 'units' in 0's --- Quote End --- you declared un as an integer but assigned a bit to it. I think you should remove the single quotation marks around the 0. --- Quote Start --- if (un <= 9) then -- check if units is less than or equal to 9 --- Quote End --- I think this should be if (un = 9) then -- check if units is less than or equal to 9 Add use ieee.std_logic_signed.all; along with what you have and recompile and let's get the feedback.