Constraint clocks of SPI interfa

Hi all,

I have a design where I generate an SPI clock and send some data over the slave. The slave is an ADC with its own setup/hold time constraints. In these constraints, the slave data input SDI has constraints with respect to the SCLK, but I'm not sure how to properly constraint that. What I did so far is that I constrainted the SCLK on its own as if it's a data output of the FPGA and then constraint the MOSI with referencing the SCLK. The syntax I used in the sdc file is added below.

# main clock of the FPGA
create_clock -name {clk} -period 100MHz [get_ports {clk}]

# Specify generated clock from PLL (PLL output is 100MHz)
# set_instance_assignment -name corepll_inst|altpll_component|auto_generated|pll1 -to pll_inst
# create_generated_clock -name {pll_clk} -source [get_pins pll_inst|clk[0]] -divide_by 1

# constraints for SCLK and MOSI
set_output_delay -clock {corepll_inst|altpll_component|auto_generated|pll1|clk[0]} -max  3 [get_ports {SCLK1}]
set_output_delay -clock {corepll_inst|altpll_component|auto_generated|pll1|clk[0]} -min -2 [get_ports {SCLK1}]
set_output_delay -clock {corepll_inst|altpll_component|auto_generated|pll1|clk[0]} -reference_pin SCLK1 -max  5  [get_ports {MOSI1}]
set_output_delay -clock {corepll_inst|altpll_component|auto_generated|pll1|clk[0]} -reference_pin SCLK1 -min -5  [get_ports {MOSI1}]

What I observe in the Timing Analyzer is that the setup and hold times are not the only things when checking the timing analyzer. For the example that you can see on the snippet attached, I would expect that the data required for the setup time of SCLK1 would be only 3 ns far from the latch clock's posedge, where the cursor is. I'm almost sure that what I want to achieve does not match with the constraints I used, therefore I'd like to ask what I'm doing wrong or missing.

Any help is much appreciated,

Cheers