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anonimcs's avatar
anonimcs
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2 years ago
Solved

Constraint clocks of SPI interfa

Hi all, I have a design where I generate an SPI clock and send some data over the slave. The slave is an ADC with its own setup/hold time constraints. In these constraints, the slave data input SDI ...
Timing
  • anonimcs's avatar
    anonimcs
    2 years ago

    Adding the pins of the Quad SPI IP did not work, but generating another clock like this and constraining the other QSPI ports wrt. this clock seems to work somehow

    create_generated_clock -name {qclk_vclk} -source [get_pins {corepll_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_ports {QSPI_CLK}]
TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

I'm not really quiet understand what you mean by 'use the sclk1 outputs to check the timing of some certain ports'. Based on the current SDC file the main problem is the clocks you created are ignored.

If you want to create a virtual clock you can use the 'create_clock' constraint.


  • anonimcs's avatar
    anonimcs
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    2 years ago

    What I meant by that is this: I want the SCLK1 clock output to be used for checking the setup/hold time violations of MOSI1 and MISO1 ports for example. The setup/hold time requirements are given by the manufacturer of the external chip. But at the same time, I want to check SCLK1, MISO1 and MOSI1 with respect to the pll clock to verify that the timing is right for the FPGA itself as well as the external device.