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anonimcs
Contributor
ContributorConstraint clocks of SPI interfa
Hi all, I have a design where I generate an SPI clock and send some data over the slave. The slave is an ADC with its own setup/hold time constraints. In these constraints, the slave data input SDI ...
Adding the pins of the Quad SPI IP did not work, but generating another clock like this and constraining the other QSPI ports wrt. this clock seems to work somehow
create_generated_clock -name {qclk_vclk} -source [get_pins {corepll_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_ports {QSPI_CLK}]
TingJiangT_IntelContributor
ContributorI upload the user guide here
anonimcsContributor
ContributorHi @TingJiangT_Intel ,
I don't get how I can do what I've described in this entry with virtual clocks then. Because I wanted to use the sclk1 outputs to check the timing of some certain ports. What would be the right approach here ?
