Forum Discussion
ContributorConstraint clocks of SPI interfa
Adding the pins of the Quad SPI IP did not work, but generating another clock like this and constraining the other QSPI ports wrt. this clock seems to work somehow
create_generated_clock -name {qclk_vclk} -source [get_pins {corepll_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_ports {QSPI_CLK}]
ContributorCurrently, you output/input delay constraints are invalid due to the previous problem we discussed which caused these paths unconstraint, and the software won't analyze these paths.
You need to first fix the issue of ignored constraints.
Please apply 'set_instance_assignment -name corepll_inst|altpll_component|auto_generated|pll1 -to pll_inst' to the qsf file instead of sdc file. Or you can directly use 'corepll_inst|altpll_component|auto_generated|pll1' instead of pll_inst.
And don't use get_fanin to get the source clock, please try to use wire_pll1_clk[0]~clkctrl as the source clock of qclk.
I can't apply changes to your sdc file, so please try the modification from your side.
Hope this can help.
- anonimcs
Should I use `get_nets` then to use that wire ?
