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anonimcs's avatar
anonimcs
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2 years ago
Solved

Constraint clocks of SPI interfa

Hi all, I have a design where I generate an SPI clock and send some data over the slave. The slave is an ADC with its own setup/hold time constraints. In these constraints, the slave data input SDI ...
Timing
  • anonimcs's avatar
    anonimcs
    2 years ago

    Adding the pins of the Quad SPI IP did not work, but generating another clock like this and constraining the other QSPI ports wrt. this clock seems to work somehow

    create_generated_clock -name {qclk_vclk} -source [get_pins {corepll_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_ports {QSPI_CLK}]
TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

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