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Altera_Forum
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14 years ago

connecting a single output to a bus

Hello everyone, I am a beginner at FPGA and I'm pretty much stuck with what I think is a basic problem. I can't extract a single signal from a bus. I have data[7..0] and graphically connected an output to it, right clicked > properties and named it Data[0]. I have done the same with every line in the bus (Data[1], Data[2]...) but the compiler comes back with

Error: Width mismatch in Data[0] -- source is ""Data[7..0]" (ID nt174:inst18)".. I'm sure I'm doing something stupid but can't quite figure out what is wrong. Thanks to everyone in advance and once I'm up to speed, I hope to give back in the future.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    If this is the graphical editor, you need to do named association to get individual bits out of a bus. You cannot simply connect them.

    Just leave them physically disconnected, but name the single bit line as Data[0], data[1] etc. It will connect them for you when compiling (even thhough they stay disconnected in the diagram).
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks Tricky, it works! I compiled and gives no errors, i tried it on the FPGA and it works too. I wonder if there is a way of graphically connecting these lines to the bus, even after compilation. It is way much clearer to see lines connected to something than just seeing the named inputs.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I think you can do it with the Wire block, but I think you still need the names.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    Thanks Tricky, it works! I compiled and gives no errors, i tried it on the FPGA and it works too. I wonder if there is a way of graphically connecting these lines to the bus, even after compilation. It is way much clearer to see lines connected to something than just seeing the named inputs.

    --- Quote End ---

    You can connect with the bus tool and then make sure the pin name has enough pins with the .. notation. For example for 8 pins use dataout[7..0].
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    You could also try with the Verilog coding or VHDL coding which I believe it should be simpler to extracting single data bit from a bus.