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Altera_Forum
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14 years ago

connecting a single output to a bus

Hello everyone, I am a beginner at FPGA and I'm pretty much stuck with what I think is a basic problem. I can't extract a single signal from a bus. I have data[7..0] and graphically connected an outp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks Tricky, it works! I compiled and gives no errors, i tried it on the FPGA and it works too. I wonder if there is a way of graphically connecting these lines to the bus, even after compilation. It is way much clearer to see lines connected to something than just seeing the named inputs.