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Altera_Forum's avatar
Altera_Forum
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12 years ago

Connect between Blocks at VHDL

Hi ,

i'm starting my final BS.c project and i'm doing it at Quartos and VHDL .

I have blocks that i design at vhdl and i want to connect between them (logicly) ,

i know that there is an option to define each block as a component at different file and define each block at the top file of the project

and make instantiation at the top file .

Is this the right solution of doing it ?

Does instantiation means to connect between to components or connect between signal to I/O port and vice versa ?

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    When you instantiate a component you can map its inputs and output to the inputs and output of the top level entity or to internal signals. To connect the signal of 2 components use internal signals. I post a code of a circuit based on nand gates. This gates were implemented in a different component and instantiated many times. It's only for academic purposes.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    appreciate your answer ,

    Few more questions :

    what do i write at the top level entity ? is it the entity declaration and Instantiation and interconnections ?

    where do i write the design of the entity ? at other file or at the same file ?

    Thank you very much !
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    First you create a Quartus project with a name, say it "toto" for example. usually you give the same name to the top level entity:

    entity toto is....

    if you give a different, an error appears during compilation saying that can't find top level entity. Go to Assignments->Setting->general and select the top level entity from the box "Top-level entity".

    Below the entity declaration, in same fiel, u write the architecture ( what you called the design of the entity ). Here you place the instantiation of the component ( entities located in diffent files. All files must be added to the project ).
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I understand ,

    At the files that you sent me there weren't components , just entities ; then at the second file you wrote the architecture .

    can i work that way ? without components ? and then write the architecture of the entities at different files ?

    thanks bertulus .
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    No. All files has an entity declaration and a architecture. The entity defines a circuit as a black box and architecture says what are inside the box.

    For example if you design a not gate:

    entity not_gate is

    port(

    ent : in std_logic;

    sal : out std_logic

    );

    end entity not_gate;

    architecture some_name_of_arch of not_gate is

    -- signals declarations

    begin

    sal <= not ent;

    end architecture some....

    u use this structure in all vhdl files.

    Second. The code seems that i not use component. i used without explicitily saying. In the line:

    nand_1: entity work.nand_3 (implementacion)

    port map( i1 => b , i2 => c , i3 => d , o => g );

    I'm using entity nand3 as a component. In the old fashion vhdl you have to declare a component with the "component" reserved word, and then use it. It's a wordy way of use components. In modern vhdl you can use an entity as a component not declared previously.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thank you very much bertulus ,

    you made it look very easy with your explanation ,

    appreciate it so much ,

    odedidush .
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Actually, components are still needed when you do mixed code instantiation (say VHDL isntantiating AHDL or Verilog) or a black box. Using direct instantiation makes the compiler check the entity, which means missmatches are picked up soon. If you use a component, the missmatch wont appear until it tries to map the component to an entity at the elaboration stage, which could be 10 minutes later in a large compile.