Connect between Blocks at VHDL

Actually, components are still needed when you do mixed code instantiation (say VHDL isntantiating AHDL or Verilog) or a black box. Using direct instantiation makes the compiler check the entity, which means missmatches are picked up soon. If you use a component, the missmatch wont appear until it tries to map the component to an entity at the elaboration stage, which could be 10 minutes later in a large compile.