Connect between Blocks at VHDL

No. All files has an entity declaration and a architecture. The entity defines a circuit as a black box and architecture says what are inside the box.

For example if you design a not gate:

entity not_gate is

port(

ent : in std_logic;

sal : out std_logic

);

end entity not_gate;

architecture some_name_of_arch of not_gate is

-- signals declarations

begin

sal <= not ent;

end architecture some....

u use this structure in all vhdl files.

Second. The code seems that i not use component. i used without explicitily saying. In the line:

nand_1: entity work.nand_3 (implementacion)

port map( i1 => b , i2 => c , i3 => d , o => g );

I'm using entity nand3 as a component. In the old fashion vhdl you have to declare a component with the "component" reserved word, and then use it. It's a wordy way of use components. In modern vhdl you can use an entity as a component not declared previously.