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IsaacQuebec's avatar
IsaacQuebec
Icon for New Contributor rankNew Contributor
2 years ago

Confusion about RTL viewer of Verilog Code: DATAIN of a latch has no connection

I'm a newbie to FPGA design and Quartus ii. I am quite puzzled about the synthesis results of the following code.

Here is the code:

module sram(Din, CS, WR, Dout);
input CS, WR; // CS: chip select, active low
input Din;
output Dout;
reg Dout;
always @(CS or WR or Din)
if (!CS)
if (WR)
Dout=Din;
else
Dout=Dout;
else
Dout=1'bz;
endmodule

The synthesis result (viewed with RTL viewer, Quartus ii 18.0) is:

I don't understand why the DATAIN input port of latch Dout_14 is not connected to anything. In this case, what should be the output of Dout_14 when CS = 0? I wonder if it is really a normal latch that I know. Is there any way to get detailed description of a node in RTL viewer including its input/output ports, its behavioural in Quartus ii?

Simulation

5 Replies

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    Thanks for using Intel Communities.

    Please allow some time while I investigate your problem.


    Regards,

    Nurina


  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Hi,
    I suggest to look at post-mapping netlist to see the actual implementation.

    As far as I understand, the shown code doesn't implement a latch, because Dout isn't necessarily hold with nCS = 1.

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    It seems like the output of Dout_14 just acts as an enable signal for the tri-state buffer, so it doesn't need a DATAIN.

    You can do an RTL simulation if you want to check what happens when CS='0'.


    If the synthesized circuit is not what you wanted, I suggest you use the available templates for latch, Quartus has a latch primitive. You can go to the text editor, right-click and select Insert Template>Verilog HDL>Altera Primitives>LATCH.


    Regards,

    Nurina


  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Or stop using latches and use registers instead. Best practice for FPGA designs should be focused on RTL (register transfer level) design. Using latches uses additional resources and makes it difficult to meet timing requirements.

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    We have not received a reply from you. As such, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

    Have a great day!

    Best regards,

    Nurina W.