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IsaacQuebec's avatar
IsaacQuebec
Icon for New Contributor rankNew Contributor
2 years ago

Confusion about RTL viewer of Verilog Code: DATAIN of a latch has no connection

I'm a newbie to FPGA design and Quartus ii. I am quite puzzled about the synthesis results of the following code. Here is the code: module sram(Din, CS, WR, Dout); input CS, WR; // CS: chip selec...
Simulation
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Or stop using latches and use registers instead. Best practice for FPGA designs should be focused on RTL (register transfer level) design. Using latches uses additional resources and makes it difficult to meet timing requirements.