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IsaacQuebec's avatar
IsaacQuebec
Icon for New Contributor rankNew Contributor
2 years ago

Confusion about RTL viewer of Verilog Code: DATAIN of a latch has no connection

I'm a newbie to FPGA design and Quartus ii. I am quite puzzled about the synthesis results of the following code. Here is the code: module sram(Din, CS, WR, Dout); input CS, WR; // CS: chip selec...
Simulation
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


It seems like the output of Dout_14 just acts as an enable signal for the tri-state buffer, so it doesn't need a DATAIN.

You can do an RTL simulation if you want to check what happens when CS='0'.


If the synthesized circuit is not what you wanted, I suggest you use the available templates for latch, Quartus has a latch primitive. You can go to the text editor, right-click and select Insert Template>Verilog HDL>Altera Primitives>LATCH.


Regards,

Nurina