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IsaacQuebec's avatar
IsaacQuebec
Icon for New Contributor rankNew Contributor
3 years ago

Confusion about RTL viewer of Verilog Code: DATAIN of a latch has no connection

I'm a newbie to FPGA design and Quartus ii. I am quite puzzled about the synthesis results of the following code. Here is the code: module sram(Din, CS, WR, Dout); input CS, WR; // CS: chip selec...
Simulation
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


We have not received a reply from you. As such, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Nurina W.