Component syntax error - help fast

I would recode it as

COMPONENT DIVIDER

PORT ( NUMERATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

DENOMINATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

QUOTIENT: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

REMAINDER: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

);

END COMPONENT;

Note each port is a single declaration

I think the "Is" after the component declaration is only valid from VHDL 93, so you need to check that you are compiling for 93 not 87

So for 87 use the following

COMPONENT DIVIDER

...

END COMPONENT;

and for 93 use the following

COMPONENT DIVIDER IS

...

END COMPONENT DIVIDER;

Also, check you have included the correct libraries atthe start of the file

library IEEE;

use IEEE.STD_LOGIC_1164.all;

Hope this helps

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I would recode it as

COMPONENT DIVIDER

PORT ( NUMERATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

DENOMINATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

QUOTIENT: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

REMAINDER: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

);

END COMPONENT;

Note each port is a single declaration

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Actually, now I am not sure if this makes a difference. I always break each port out onto a separate declaration but thinking about it again it should be OK. I reckon it's more likely to be the VHDL 87/93 issue I described

Hi,

I can see an inferred multiplication on port map. Can you do that?

I think port map is for wiring only. You better do the multiplication somewhere else and preferably in a clocked process.

kaz

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I can see an inferred multiplication on port map. Can you do that?

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Yes, the shown code would be completely accepted by Quartus with use ieee.std_logic_unsigned.all in effect, if appearing at the right place of a design, of course with the required signal and library definitions. I guess, it's just an overall design syntax problem. As said, not understandable from a snippet.

Hi,

However, I see it very odd to infer a mult on an instantiation of a divider...would fellow ModelSim accept it? I doubt it.

Note also that the last odd statement in port declaration should not have semicolon(second post).

Kaz

However, I see it very odd to infer a mult on an instantiation of a divider...would fellow

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ModelSim accept it? I doubt it.

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No ModelSim doesn't accept it. I confess, that I was surprized Quartus does, but I tried.

Also, I wouldn't use positional association, cause it's highly susceptible for parameter mix-up.

From memory, later versions (perhaps 2000 or 2002) of VHDL do accept operators in a port map.

In your port list in the component declaration, I don't think the last port (REMAINDER) should have a semi-colon at the end.