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Altera_Forum
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17 years ago

Component syntax error - help fast

COMPONENT DIVIDER IS PORT ( NUMERATOR, DENOMINATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 ); QUOTIENT, REMAINDER: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 )); END COMPONENT; MODULE2: DI...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

I can see an inferred multiplication on port map. Can you do that?

I think port map is for wiring only. You better do the multiplication somewhere else and preferably in a clocked process.

kaz