Component syntax error - help fast

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I would recode it as

COMPONENT DIVIDER

PORT ( NUMERATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

DENOMINATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

QUOTIENT: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

REMAINDER: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

);

END COMPONENT;

Note each port is a single declaration

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Actually, now I am not sure if this makes a difference. I always break each port out onto a separate declaration but thinking about it again it should be OK. I reckon it's more likely to be the VHDL 87/93 issue I described