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Altera_Forum
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17 years ago

Component syntax error - help fast

COMPONENT DIVIDER IS PORT ( NUMERATOR, DENOMINATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 ); QUOTIENT, REMAINDER: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 )); END COMPONENT; MODULE2: DI...
Altera_Forum's avatar
Altera_Forum
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17 years ago

From memory, later versions (perhaps 2000 or 2002) of VHDL do accept operators in a port map.

In your port list in the component declaration, I don't think the last port (REMAINDER) should have a semi-colon at the end.