Component syntax error - help fast

I would recode it as

COMPONENT DIVIDER

PORT ( NUMERATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

DENOMINATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

QUOTIENT: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

REMAINDER: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

);

END COMPONENT;

Note each port is a single declaration

I think the "Is" after the component declaration is only valid from VHDL 93, so you need to check that you are compiling for 93 not 87

So for 87 use the following

COMPONENT DIVIDER

...

END COMPONENT;

and for 93 use the following

COMPONENT DIVIDER IS

...

END COMPONENT DIVIDER;

Also, check you have included the correct libraries atthe start of the file

library IEEE;

use IEEE.STD_LOGIC_1164.all;

Hope this helps