combinational loops as latches

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For the latches introduced by Quartus, it should be due to the optimization done by the Quartus to replace some circuit, I believe you can turn off the optimization through the Quartus -> assignment -> setting

But I still doubt the optimization introduce the warnings.

Ignore this warning might cost you more time to debug in future in the hardware, as you might see some behavior not match your expectation, and you will have difficult during debugging

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The setting for "Analysis and synthesis" is: "balanced", "Power-up don't care", and "Normal compilation". So based on all the info I posted here, can somebody figure out how to fix all these 52 warnings? That is, one bit of each 13 bits' register (totally 4 registers) has a "converting to equivalent circuit" warning.

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All the variables on the left are register variables, and on the right are inputs to this submodule or some constants. This is for the initialization for the calculation of a new group of input data. The timing is controlled by the clocks (reset, clk). Is this something related to "multiple bit asynchronous load"?

Besides, one warning for each bit for the four variables (Iplus, Qplus, Iminus, Qminus) --- 52 warnings, which says each bit is converted into an equivalent circuit using its corresponding register.

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That's a nice example of asynchronous load, so the warnings are pretty understandable. But why at all are you performing an asynchronous reset? Isn't the "initialization for the calculation of a new group of input data" executed as part of the synchronous design sequence?

I presume you know, that the reset signal must be released synchronous to clock edge, otherwise it won't load the intended values reliably.

Yes, I considered the timing for this reset and clock signals. 1. I need this reset signal to be effective before the rising edge of clock comes (e.g. occurs at the falling edge of clock of previous clock cycle). At the same time, I need this reset signal to be slower than the clock signal (e.g. 8 times slower). I am sorry that I am new on this part. Any advise on how to fix this problem? Any tutorial on the asynchronous and synchronous design?

I did such a design because I need 8 loops of calculation for each group of input data. Then the iteration needs to be reset with some new inputs for another round of calculation (8 loops again). Therefore, I use "clock" to control the loops and "reset" to control the update of the input data.

Please do advise on how to fix the problem and any related tutorial. Thanks in advance.

Again, seek solutions for the above problem in this thread...

Thanks in advance!

I cant really see any loop here...

the right side you mention is input to the submodule, is it input from top level, or where are they from

The loops are clicked by the rising edge in the else block. Yes, it is from the top level.

However, I simply decided to use synchronous bit loading, which has eliminated all the latches. Thanks.