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All the variables on the left are register variables, and on the right are inputs to this submodule or some constants. This is for the initialization for the calculation of a new group of input data. The timing is controlled by the clocks (reset, clk). Is this something related to "multiple bit asynchronous load"?
Besides, one warning for each bit for the four variables (Iplus, Qplus, Iminus, Qminus) --- 52 warnings, which says each bit is converted into an equivalent circuit using its corresponding register.
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That's a nice example of asynchronous load, so the warnings are pretty understandable. But why at all are you performing an asynchronous reset? Isn't the "initialization for the calculation of a new group of input data" executed as part of the synchronous design sequence?
I presume you know, that the reset signal must be released synchronous to clock edge, otherwise it won't load the intended values reliably.
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