combinational loops as latches

Yes, I considered the timing for this reset and clock signals. 1. I need this reset signal to be effective before the rising edge of clock comes (e.g. occurs at the falling edge of clock of previous clock cycle). At the same time, I need this reset signal to be slower than the clock signal (e.g. 8 times slower). I am sorry that I am new on this part. Any advise on how to fix this problem? Any tutorial on the asynchronous and synchronous design?

I did such a design because I need 8 loops of calculation for each group of input data. Then the iteration needs to be reset with some new inputs for another round of calculation (8 loops again). Therefore, I use "clock" to control the loops and "reset" to control the update of the input data.

Please do advise on how to fix the problem and any related tutorial. Thanks in advance.