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For the latches introduced by Quartus, it should be due to the optimization done by the Quartus to replace some circuit, I believe you can turn off the optimization through the Quartus -> assignment -> setting
But I still doubt the optimization introduce the warnings.
Ignore this warning might cost you more time to debug in future in the hardware, as you might see some behavior not match your expectation, and you will have difficult during debugging
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The setting for "Analysis and synthesis" is: "balanced", "Power-up don't care", and "Normal compilation". So based on all the info I posted here, can somebody figure out how to fix all these 52 warnings? That is, one bit of each 13 bits' register (totally 4 registers) has a "converting to equivalent circuit" warning.
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