Clock divider

It's not a good practice to use clock divider in fpgas. Instead you should use clock enable. You may have problems if you use different math libraries like numeric_std and math_real. With numeric_std it's enough.

This is the code for a clock enable:

architecture....

signal cont_reg, cont_prox : unsigned(3 downto 0);

begin

process(n_clr, clk)

begin

if ( n_clr = '0' ) then

cont_reg <= ( others => '0' );

elsif( clk'event and clk = '1' ) then

cont_reg <= cont_prox;

end if;

end process;

cont_prox <= cont_reg + 1 when ( cont_reg < 11 ) else

( others => '0' );

clk_en <= '1' when ( cont_reg = 0 ) else

'0';

It counts from 0 to 12. You can get the 3,75MHz frequency with this approach. A clock divider could be implemented if you change last line:

clk_en <= '1' when ( cont_reg < 6 ) else

'0';

Ok I try this :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.numeric_std.all;

entity CPU_CLOCK is

port (CLK : in std_logic;

n_clr : in std_logic;

clk_en: out std_logic );

end entity CPU_CLOCK;

architecture arch of CPU_CLOCK is

signal cont_reg, cont_prox : unsigned(3 downto 0);

begin

process(n_clr, clk)

begin

if ( n_clr = '0' ) then

cont_reg <= ( others => '0' );

elsif( clk'event and clk = '1' ) then

cont_reg <= cont_prox;

end if;

end process;

cont_prox <= cont_reg + 1 when ( cont_reg < 11 ) else

( others => '0' );

clk_en <= '1' when ( cont_reg = 0 ) else

'0';

end arch;

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I found this code but it doesn't seem working with all "constant CLK_SLOW_FREQ"

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What do you mean? The code does work as a 14:1 clock divider, output is one input period high, as expectable. It could e.g. work as a clock enable in a 50 MHz clock domain.

The second code generates a similar output signal, but with 12:1 ratio, output frequency is 4.167 MHz. The coding style is unnecessarily complicated, I think. Due to the combinational generation of clk_en, the output has glitches. Either if the output is intended as clock or clock enable, I would register it. In case of the divided clock, you avoid glitches, for the clock divider, you improve setup time.

But what do you want to achieve exactly?

I need a clock divider to run a T80 core at 3,58Mhz

For the first code I tried to slow clock output to see if led blink well but I saw nothing.

This one would be handy because clock could be set precisely.

The second is to difficult to understand for me.

The best result I had for now is with a simple counter like that but I'm not sure of clk_out.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity CLOCK3_57 is

port (clk_in : in std_logic;

clk_out : out std_logic;

reset_n : in std_logic

);

end entity CLOCK3_57;

architecture Behavioral of CLOCK3_57 is

signal temporal: STD_LOGIC;

signal counter : integer range 0 to 6 := 0;

begin

frequency_divider: process (reset_n, clk_in) begin

if (reset_n = '0') then

temporal <= '0';

counter <= 0;

elsif rising_edge(clk_in) then

if (counter = 6) then

temporal <= NOT(temporal);

counter <= 0;

else

counter <= counter + 1;

end if;

end if;

end process;

clk_out <= temporal;

end Behavioral;

No problem with 50Mhz, all the system will run at 3.57Mhz except the VDP witch needs 10.69Mhz.

For this part I'll try the first code.

I use a cheap EP2C5 board, can you explain PLL if this one can do it ?

10.69MHz = 3.57MHz * 3

If you can generate 10.69MHz with the pll then you can use a clock enable scheme to slow down the z80 to the proper 3.58MHz.

Your right, it's used on a lot of real machines.

But now I don't know how to use PLL

The pll has a Wizard that guide you. It's very easy. Then you can instantiate the pll as another module:

pll_inst : pll

port map(

areset => not n_rst,

inclk0 => clk,

c0 => clk_10MHz,

locked => open

);

inclk0 is your 50MHz clock and c0 is your 10.69MHz output.

You can invoke Wizard form Quartus Tools->Megaplug in Wizard->Create a new custom variation->Select I/O folder->ALTPLL.

Yeah :-P

Very easy

Quartus doesn't want create 10.69 but accept 10.00 :confused: