Clock divider

It's not a good practice to use clock divider in fpgas. Instead you should use clock enable. You may have problems if you use different math libraries like numeric_std and math_real. With numeric_std it's enough.

This is the code for a clock enable:

architecture....

signal cont_reg, cont_prox : unsigned(3 downto 0);

begin

process(n_clr, clk)

begin

if ( n_clr = '0' ) then

cont_reg <= ( others => '0' );

elsif( clk'event and clk = '1' ) then

cont_reg <= cont_prox;

end if;

end process;

cont_prox <= cont_reg + 1 when ( cont_reg < 11 ) else

( others => '0' );

clk_en <= '1' when ( cont_reg = 0 ) else

'0';

It counts from 0 to 12. You can get the 3,75MHz frequency with this approach. A clock divider could be implemented if you change last line:

clk_en <= '1' when ( cont_reg < 6 ) else

'0';