Clock divider

I need a clock divider to run a T80 core at 3,58Mhz

For the first code I tried to slow clock output to see if led blink well but I saw nothing.

This one would be handy because clock could be set precisely.

The second is to difficult to understand for me.

The best result I had for now is with a simple counter like that but I'm not sure of clk_out.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity CLOCK3_57 is

port (clk_in : in std_logic;

clk_out : out std_logic;

reset_n : in std_logic

);

end entity CLOCK3_57;

architecture Behavioral of CLOCK3_57 is

signal temporal: STD_LOGIC;

signal counter : integer range 0 to 6 := 0;

begin

frequency_divider: process (reset_n, clk_in) begin

if (reset_n = '0') then

temporal <= '0';

counter <= 0;

elsif rising_edge(clk_in) then

if (counter = 6) then

temporal <= NOT(temporal);

counter <= 0;

else

counter <= counter + 1;

end if;

end if;

end process;

clk_out <= temporal;

end Behavioral;