Clock divider

Ok I try this :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.numeric_std.all;

entity CPU_CLOCK is

port (CLK : in std_logic;

n_clr : in std_logic;

clk_en: out std_logic );

end entity CPU_CLOCK;

architecture arch of CPU_CLOCK is

signal cont_reg, cont_prox : unsigned(3 downto 0);

begin

process(n_clr, clk)

begin

if ( n_clr = '0' ) then

cont_reg <= ( others => '0' );

elsif( clk'event and clk = '1' ) then

cont_reg <= cont_prox;

end if;

end process;

cont_prox <= cont_reg + 1 when ( cont_reg < 11 ) else

( others => '0' );

clk_en <= '1' when ( cont_reg = 0 ) else

'0';

end arch;